About

Ajith Kumar B is a highly experienced systems software developer, lead, and manager with over 14 years of experience in high-performance flash storage software, big data stack, and deep learning. He is currently building a product and team at akridata, an early-stage startup, to address challenges in edge to core AI data pipelines. Ajith has strong product development experience as an individual contributor, lead, and manager, with around 10 years at flash storage startup, Virident Systems (acquired by Western Digital). He is experienced with 'from-scratch' product development as well as exploratory research activities. Ajith has 20+ granted USPTO patents related to flash storage management and data deduplication. In his previous role at HGST, Ajith was a Global Senior Manager - SW Advance Tech Group (Research Organization), leading a software engineering team of 4 reporting to WD research organization specifically focusing on conception, design, prototyping, and evaluation of future product ideas and features related to high-performance storage technologies. Key areas of work consist of inline data reduction (compression, de-duplication) using similarity-based techniques for high-performance flash storage devices and systems, dynamic paging of flash translation structures, exploring rack level NVME-over-fabric shared storage for big data workload specifically on optimizing HDFS and Spark stack using shared storage and FPGA-based acceleration, and exploratory research on understanding system interactions of machine learning (ML) algorithms and FPGA-based acceleration of ML algorithms. Being an early member of Virident engineering team, Ajith had the opportunity to take on key technical roles and grow up progressively from an individual developer to a lead in their startup's journey towards pioneering high-performance PCI-E SSD family of products. His key involvements included the development of a custom file system for EcoRAM (NOR flash-based product) as an attempt towards enabling system-level consumption of storage class memory, development of SW layer responsible for abstracting HW level topology intricacies and providing capabilities like flash-aware IO scheduling, thermal and power monitoring, and feedback-based IO rate control at a very fine granularity, full-stack performance characterization and improvements in areas of latency reduction, eliminating various SW bottlenecks in a multi-threaded Linux kernel driver implementation, providing optimal HW level resource utilization, fine-grained IO QOS, dynamic behavior modification based on automatic workload detection for optimal performance for varying workloads, predictable and consistent performance behavior through coordination of foreground (new IO) and background (Garbage collection) activities,